1. Field of the Invention
This invention generally relates to semiconductors and writing methods, and more particularly, to a semiconductor device having a multi-level memory cell and a method for writing data into the multi-level memory cell.
2. Description of the Related Art
The semiconductor memories are categorized into volatile ones that lose the information therein and non-volatile ones that retain the information therein, when the power turns off. Flash memories, in which the rewriting time is shortened by erasing the data at one time, are well known as a representative of the non-volatile ones.
FIG. 1 is a block diagram of programming a flash memory that does not have a write buffer for SLC (Single Level Cell) therein. In this flash memory, programming is performed for each one word (16 bits). As shown in FIG. 1, a flash memory 1 includes an input buffer 2, a write latch circuit 3, write voltage applying circuit 4, a memory cell array 5, a sense amplifier circuit 6, a comparator circuit 7, and a control circuit 8. The input buffer 2 retains a user write data. The write latch circuit 3 latches the user write data applied from the input buffer 2.
The write voltage applying circuit 4 writes the data into the memory cell to be associated with the write data. The sense amplifier circuit 6 reads out the data of the memory cell in a verify period, and the comparator circuit 7 compares the read-out data with the write data input from the outside. If the memory cell is sufficiently programmed, the write latch circuit 3 inverts the write data in the latch therein, and completes programming. On the other hand, if the memory cell is not sufficiently programmed, the write latch circuit 3 continues programming. The comparator circuit 7 determines whether all bits have passed. If all the bits have passed, the control circuit 8 controls the program operation at the next level.
Also, the flash memory having MLC (Multi Level Cell) has conventionally been proposed. The product type having the multi-level cell has four threshold levels, level 1, level 2, level 3, and level 4. The higher the level becomes, the higher the threshold level is configured. The aforementioned four levels compose two kinds of output (or input) data. Generally, at the time of programming the data of level 4, the writing method of going through the level 1 through the level 3 to reach the level 4.
Patent Document 1 proposes a semiconductor memory device having a binary data register that retains the write data that has been input. In addition, Patent Document 2 proposes another semiconductor device having a data latch circuit that latches the write data applied from the outside and a sense latch circuit that latches the write control information.
Patent Document 1: Japanese Patent Application Publication No. 11-73790
Patent Document 2: Japanese Patent Application Publication No. 11-232886
Programming the multi-level memory cell, however, has a concern of over programming that exceeds the level, and programming has to be performed to increase the threshold voltage Vth little by little. In the aforementioned programming method, programming and verification have to be repeated several times, causing a problem in that a programming period increases. The devices described in Patent Document 1 and Patent Document 2 cannot solve the problem of increasing the programming period.